The present invention relates generally to integrated circuit device testing, and more specifically to parallel testing of integrated circuit devices.
Testing is performed throughout the manufacture and assembly of integrated circuit devices, such as at wafer sort where the speed grade of a device may be determined. Integrated circuit devices subjected to parallel testing are typically placed side by side on a wafer, and the pads of the integrated circuit devices are then probed by a tester in order to test the electrical soundness of the devices. Because the integrated circuit devices are placed side by side next to each other, parallel testing is performed on "ends only" devices or integrated circuit devices whose pads are arranged along the two opposite ends, and not along all four sides of the device. Typically, then, "ends only" integrated circuit devices can be small density parts, and are usually rectangular in shape having an aspect ratio defined as the length to width dimensions of the device. The pads of the device are arranged only along opposite ends of the device to easily allow for parallel testing of the integrated circuit device simultaneously with other identical integrated circuit devices. Parallel testing could additionally be performed on a square die device if it had very few pads which were arranged along just two opposite sides of the die.
Small density integrated circuit devices are often "ends only" devices by virtue of their relatively small die size and limited number of pads. These pads must be probed during testing of the device, and thus lend themselves to parallel testing. Parallel testing of small density integrated circuit devices may not be necessary. Because of the relative lack of complexity of such small density integrated circuit devices, testing may be accomplished in relatively short order and thus testing time does not pose a significant concern to manufacturers of these devices. Thus, although testing time of small density integrated circuit devices could be reduced by parallel testing of two or more "ends only" devices side by side simultaneously, this option may not be pursued where testing time is not a concern for small density integrated circuit devices.
As integrated circuit devices have become larger, more dense and complex, however, the issue of test time reduction has become increasingly important as the time required to test higher density devices has increased in proportion to the complexity of the device. A logical approach to address the issue of test time reduction, is to test more than one integrated circuit device at a time, i.e. to perform parallel testing of two or more integrated circuit devices simultaneously.
A recent trend in integrated circuit memory devices has been to make most memory densities available in a variety of packages, and more recently in packages that are 300 mils in width. This necessitates a bonding configuration similar to that seen for the 1 Meg SRAM shown in FIG. 1. The assembly requirements shown in FIG. 1 are pertinent to any 300 mil device using similar lead frames. Additionally, other package types such as a DIP (dual in-line package) or SOJ may be used. The assembly demands for a larger density integrated circuit device, such as a 1 Meg SRAM (Static Random Access Memory) shown in FIG. 1, however, often dictate the placement of distributed pads along the long dimension of the die in order to optimize bonding to the device lead frame. Larger density integrated circuit devices, then, are typically not "ends only" devices and thus are not easily adaptable to parallel testing. The large number of pads to be tested in larger density and complex devices simply can not all be placed just along two opposite ends of the device. Thus, while large density integrated circuit devices could benefit from the reduced test time offered by parallel testing, the non- "ends only" configuration characteristic of most large density integrated circuit devices does not really allow for parallel testing.